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POWER MANAGEMENT Description
The SC1218 is a high speed, robust, dual output driver to drive high-side and low-side N-MOSFETs in synchronous buck converters. Combined with Semtech's multi-phase PWM controller SC2649, one can build high performance, versatile voltage regulators for next generation microprocessors. SC1218 is built upon a CMOS technology which provides enough voltage capacity to handle computer applications. In addition, the advanced timing circuitry is adopted to filter out very narrow PWM pulses at the input of the driver. The latched UVLO and enhanced adaptive shoot-through protection further enhance the robustness of the SC1218. With integrated bootstrap diode, the SC1218 is offered in both SOIC-8 package and MLPQ-8 3x3mm package. These features further reduce the thermal stress and BOM cost.
High Speed Synchronous MOSFET Driver
Features
Advanced Digital Timing to Filter Out Very Narrow PWM Pulses +12V Gate Drive Voltage Integrated Bootstrap Diode High Peak Drive Current Adaptive Non-overlapping Gate Drives Provide Shootthrough Protection Support Dynamic VID operation Ultra-low Propagation Delay Floating Top Gate Drive Crowbar Function for Over Voltage Protection High Frequency (up to 2 MHz) Operation Allows Use of Small Inductors and Low Cost Ceramic Capacitors Under Voltage Lockout Low Quiescent Current Enable Function for Both Gate OFF Shut Down Lead-free Part and Fully WEEE and RoHS Compliant
SC1218
Applications
Intel Next Generation Processor Power Supplies AMD AthlonTM and AMD-K8TM Processor Power
Supplies
High Current Low Voltage DC-DC Converters
Typical Application Circuit
VIN
Cbst 1uF BST TG DRN PGND BG
Mtop Cin
Rdrn (optional) Mbot
Lout
VOUT
PWM EN Rv in 2R2
CO EN VIN Cv in 1uF
SC1218
Cout
Revision: October 14, 2005
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SC1218
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VIN Supply Voltage BST to DRN BST to VIN TG to DRN TG to DRN Pulse BST to PGND BST to PGND Pulse DRN to PGND DRN to PGND Pulse BG to PGND BG to PGND Pulse PWM Input Enable Input Continuous Pow er Dissipation TA=25oC, TJ=125oC Thermal Resistance Junction to Case Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol VI N VBST-DRN VBST-VIN VTG-DRN VTG-DRN-PULSE VBST-PGND VBST-PGND-PULSE VDRN-PGND VDRN-PGND-PULSE VBG-PGND VBG-PGND-PULSE CO EN PD
Conditions
Maximum -0.3 to 16 -0.3 to 16 -0.3 to 16 -0.3 to 16
Units V V V V V V V V V V V V V V W
VPEAK w ith tPULSE < 20ns(1)
-2 -0.3 to VIN+16
tPULSE <20ns VBST-VDRN = 10V VPEAK w ith tPULSE < 200ns(1) VPEAK w ith tPULSE < 20ns(1)
38 -2 to VIN+16 -5 to 35 -8 to 35 -0.3 to VIN+0.3
VPEAK w ith tPULSE < 20ns(1)
-3.5 -0.3 to VIN+0.3 -0.3 to VIN+0.3
SOIC-8 MLPQ-8 SOIC-8 MLPQ-8
0.5 2.56 40 8 0 to 150 -65 to 150
o
JC
TJ TSTG TLEAD
C/W
o o o o
C C C C
SOIC-8 MLPQ-8
300 260
Notes: (1) Pulse width measured at 10% of the triangular spike waveform. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Electrical Characteristics
Unless specified: TA = 25C; VIN = 12V.
Parameter Power Supply Supply Voltage
Symbol
Conditions
M in
Typ
M ax
Units
VI N EN=5V; CO=0V
5
12 3.35 2.9 1.35
14 4.4 4 2.5
V mA mA mA
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VI N Quiescent Current
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IQ
EN=5V; CO=5V EN=0V
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SC1218
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C; VIN = 12V.
Parameter Under Voltage Lockout Start Threshold of VIN Voltage Hysteresis EN Logic High Input Voltage Logic Low Input Voltage CO Logic High Input Voltage Logic Low Input Voltage Internal Pull-down Resistor High Side Driver (TG) Output Impedence
Symbol
Conditions
M in
Typ
M ax
Units
VIN_START VhysUVLO
4 250
4.3
V mV
VEN_H VEN_L
2.65 0.8
V V
VCO_H VCO_L
2.9 0.8 40
V V Kohm
RSRC_TG RSINK_TG ISRC_TG_PK ISINK_TG_PK tPDH_TG tPDL_TG tON_MIN_TG
VBST-VDRN= 12V VIN=12V, CTG=10nF VIN=12V, CTG=10nF VBST-VDRN= 12V VBST-VDRN= 12V For CO pulse width < 40ns
1.68 0.52 2.8 6.5 37 50 40
2.1 0.78
Oh m Oh m A A ns ns ns
Output Peak Current Propagation Delay, TG Going High Propagation Delay, TG Going Low TG Minimum On-time(1) Low Side Driver (BG) Output Impedence
RSRC_BG RSINK_BG ISRC_BG_PK ISINK_BG_PK tPDH_BG tPDL_BG tOFF_MIN_BG tDH_MAX_BG
VIN = 12V VIN=12V, CBG=10nF VIN=12V, CBG=10nF VIN = 12V VIN = 12V For CO pulse width < 40ns From CO=Low, VDRN>1V
1.36 0.52 3.5 7.5 20 27 140 175
2.0 0.78
Oh m Oh m A A ns ns ns ns
Output Peak Current Propagation Delay, BG Going High Propagation Delay, BG Going Low BG Minimum OFF-time(1) BG Maximum Turn ON Delay(1)
NOTE: (1). Guaranteed by design.
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SC1218
POWER MANAGEMENT Timing Diagrams
CO TG
VCO_HI
VCO_LO
tPDH_TG BG tPDL_BG DRN
VIN & EN
VIN>UVLO & EN="HI"
tPDL_TG
1.4V
tPDH_BG
1.0V
Rising Edge Transition
Falling Edge Transition
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SC1218
POWER MANAGEMENT Pin Configuration
SOIC-8 Top View MLPQ-8 3x3mm Top View
BST TG
BST CO EN VIN
1 2 3 4
8 7 6 5
TG DRN PGND BG
CO EN
1 2
8
7 6 5
DRN PGND
3
4
VIN BG
EXPOSED PAD MUST BE SOLDERED TO POWER GROUND PLANE
Pin Descriptions
SOIC-8 1 2 3 4 5 6 M LPQ-8 8 1 2 3 4 5 Pin Name BST CO EN VIN BG PGND Pin Function Bootstrap supply pin for the top gate drive. Connect a 1uF ceramic capacitor between BST and DRN pin to develop a floating bootstrap voltage for the high side driver. PWM input signal from external controller. An internal 40Kohm resistor is connected from this pin to the PGND. When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced low. Supply power for the bottom gate driver and the internal control circuitry. Connect to input power rail of the converter and dcouple with a 1F ceramic with lead length no more than 0.2" (5mm). Output gate drive for the bottom (synchronous) MOSFET. An internal 20Kohm resistor is connected from this pin to PGND. Supply power ground return. Keep this pin close to the bottom MOSFET source during layout. Connect this pin to the power phase node of the synchronous buck converter (source of top MOSFET and drain of bottom MOSFET). The DRN pin provides a return path for top gate drive. Its voltage is deteced for adaptive shoot-through protection. This pin is subjected to a negative spike of -8V relative to PGND without affecting the operation. An internal 20Kohm resistor is connected from this pin to PGND. Output gate drive for the top (switching) MOSFET.
7
6
DRN
8
7
TG
Ordering Information
Device SC1218STRT (1)(3) SC1218MLTRT (2)(3) Package SOIC-8 MLPQ-8 Temp Range (TJ) 0 to 150C 0 to 150C
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Only available in tape and reel packaging. A reel contains 3000 devices. (3) Devices are lead-free and fully WEEE and RoHS compliant.
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SC1218
POWER MANAGEMENT Block Diagram
VIN
BST
UVLO
TG EN CONTROL & OVERLAP PROTECTION CIRCUIT
R
DRN
R
CO
BG PGND
R
Typical Performance Characteristics
CO
CO TG
TG
BG
BG
Fig. 1. TG Rise and BG Fall Times
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Fig. 2. TG Fall and BG Rise Times
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SC1218
POWER MANAGEMENT Typical Performance Characteristics (Cont.)
20 VIN=12V CLoad=3.3nF 19 TG
25
VIN=12V TA=25C
20 FALL TIME (ns)
BG
TG BG
RISE TIME (ns)
18
15
17
10
16
5
15 0 25 50 75 100 125 TEMPERATURE (C)
0 0 2 4 6 8 10 LOAD CAPACITANCE (nF)
Fig. 3. TG and BG Rise Times vs. Temperature.
11
Fig. 6. TG and BG Fall Times vs. Load Capacitance.
160
VIN=12V CLoad=3.3nF TG
SUPPLY CURRENT (mA)
VIN=12V CLoad_TG=3.3nF CLoad_BG=3.3nF TA=25C
140 120 100 80 60 40 20
10 FALL TIME (ns)
9 BG 8
7
6 0 25 50 75 100 125 TEMPERATURE (C)
0 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (KHz)
Fig. 4. TG and BG Fall Times vs. Temperature.
50
Fig. 7. Supply Current vs. Frequency.
VIN=12V TA=25C
27 TG SUPPLY CURRENT (mA) 26
VIN=12V CLoad_TG=3.3nF CLoad_BG=3.3nF Freq.=200KHz
40 RISE TIME (ns)
BG
30
25
20
24
10
23
0 0 2 4 6 8 10 LOAD CAPACITANCE (nF)
22 0 25 50 75 100 125 TEMPERATURE (C)
Fig. 5. TG and BG Rise Times vs. Load Capacitance.
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Fig. 8. Supply Current vs. Temperature.
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SC1218
POWER MANAGEMENT Typical Performance Characteristics (Cont.)
4.5 4.0 3.5 3.0 ISRC_PK (A) 2.5 2.0 1.5 1.0 0.5 0.0 5 6 7 8 9 10 11 12 13 14 VIN (V) ISINK_PK (A) TG CLOAD_TG=10nF CLOAD_BG=10nF TA=25C BG 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 5 6 7 8 9 10 11 12 13 14 VIN (V) C LOAD_TG=10nF C LOAD_BG=10nF TA=25C BG TG
Fig. 9. Peak Sourcing Current vs. Supply Voltage.
Fig. 10. Peak Sinking Current vs. Supply Voltage.
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SC1218
POWER MANAGEMENT Applications Information
THEORY OPERATION THEORY OF OPERATION The SC1218 is a high speed, robust, dual output driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features internal bootstrap diode, adaptive delay for shoot-through protection, 12V gate drive voltage, and disable shutdown. It also supports dynamic VID operation and CROWBAR function. This driver combined with PWM controller SC2649 forms a multi-phase voltage regulator for advanced microprocessors. Startup UVLO Star tup and UVLO To startup the driver, a supply voltage is applied to the VIN pin of the SC1218. The top and bottom gates are held low until VIN exceeds the UVLO threshold of the driver, typically 4.0V. The UVLO threshold has hysteresis, typically -250mV, to improve the nosie immunity from the VIN pin. Gate Transition Shoot-thr t-through Pro Gate Transition and Shoo t-through Pro t ection Refer to the Timing Diagrams section, the rising edge of the PWM input initiates the turn-off of bottom FET and the turn-on of top FET. After a short propagation delay (tPDL_BG) from PWM rising edge, the bottom gate falls (tF_BG). The adaptive circuit in the SC1218 detects the bottom gate voltage. It holds the top gate off until the bottom gate voltage drops below 1.4V for a preset delay time (tPDH_TG). This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, depended on the direction of the inductor current. The phase node could be low (ground) or high (VIN). The falling edge of the PWM input controls the turn-off of top FET and the turn-on of bottom FET. After a short propagation delay (tPDL_TG) from PWM falling edge, the top gate falls (tF_TG). As the inductor current commutates from the top FET to the body diode of the bottom FET, the phase node falls. The adaptive circuit in the SC1218 detects the phase node voltage. It holds the bottom FET off until the phase node voltage drops below 1.0V. This prevents the top and bottom FETs from conducting simultaneously (shoot-through). If the phase node voltage remains high during the transition for a preset maximum BG turn on delay (tDH_MAX_BG) , then the bottom gate will be turned on. This supports the CROWBAR function and the sinking current capacity required from dynamic VID operation. Narrow PWM Pulse Filtering During a load transient, soft start, or soft shutdown of the voltage regulator, the PWM controller may generate a very
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narrow pulse for the driver. The pulse is so narrow that it reaches the rising edge threshold of the SC1218 at one point then immediately falls below the falling edge threshold. To prevent the SC1218 from reacting to such narrow PWM pulses, which may cause driver output ringing or shoot through, advanced PWM timing circuitry is added to ease the gate transitions. A minimum off-time (typically 140ns) for the bottom gate and a minimum on-time (typically 40ns) for the top gate are enforced to make the operation safe under such conditions. Dynamic VID Operation Some processors changes VID dynamically during operation (Dynamic VID operation). A dynamic VID can occur under light load or heavy load conditions. At light load, it can force the converter to sink current. After turn-off of the top FET, the reversed inductor current flows through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high and voids the adaptive circuit. SC1218 features a maximum BG turn on delay (tDH_MAX_BG) to override the adaptive delay to turn the bottom FET on. The preset maximum BG turn on delay time (tDH_MAX_BG) from the PWM falling egde to the bottom gate turn-on is set to be 175ns. Frequency, Inductor requency MOSFETs Switching Freq uency, Inductor and MOSFETs The SC1218 is capable of providing more than 3.5A peak drive current, and operating up to 2MHz PWM frequency without causing thermal stress on the driver. The selection of switching frequency, together with inductor and FETs is a trade-off between the cost, size, and thermal management of a multi-phase voltage regulator. Typically, these parameters could be in the range of: a) Switching Frequency: 100kHz to 500kHz per phase b) Inductor Value: 0.2uH to 2uH c) MOSFETs: 4mOhm to 20mOhm RDS(ON) and 20nC to 100nC total gate charge Bootstrap and Chip Decoupling Capacitors The top gate driver of the SC1218 is a DRN refered gate drive whose supply voltage is derived from a bootstrap circuit comprising a capacitor,CBST, and a built-in diode. The capacitor value can be calculated based on the total gate charge of the top FET, QTOP, and an allowed voltage ripple on the capacitor, VBST, in one PWM cycle:
C BST > QTOP VBST
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SC1218
POWER MANAGEMENT Applications Information (Cont.)
POWER DISSIPATION (mW)
Typically, a 1uF/16V ceramic capacitor is used. In addition, a small resistor (one ohm) is recommended in between DRN pin of the SC1218 and the phase node. The resistor is used to alleviate the stress of the SC1218, resulting from the negative spike at the phase node, and also to control the switching speed. A negative spike could occur at the phase node during the top FET turn-off due to parasitic inductance in the switching loop. The spike could be minimized with a careful PCB layout. In the applications with TO-220 package FETs, it is suggested to use a clamping diode on the DRN pin to mitigate the impact of the excessive phase node negative spikes. For VIN pin of the SC1218, it is recommended to use a 1uF/16V ceramic capacitor for decoupling. Driver Dissipation and Junction Temperature Driver Tem emperature The driver power dissipation is a function of chip quiescent current IQ, switching frequency FSW, and supply voltage VIN. It is approximated as:
PD = ( I Q + QTOTAL FSW ) VIN
The typical layout examples of SC1218 based on above guidelines are shown in Fig.12 and Fig.13.
1000 Fsw=600kHz 800
600 Fsw=400kHz
400 Fsw=200kHz 200
0 40 60 80 100 120 TOTAL GATE CHARGE (nC)
Fig. 11. Power dissipation.
C CBST
To top FET
RDRN
where QTOTAL is the total gate charge of the top-side and bottom-side FETs. The power dissipation vs total gate charge at the given switching frequency is plotted in Fig.11. The driver junction temperature can be calculated based on the juntion to case thermal resistance and Printed Circuit Board (PCB) temperature. LAY LAYOUT GUIDELINES The switching regulator is a high di/dt and dv/dt power circuit. PCB layout is critical. A good layout can achieve optimum circuit performance with minimized component stress, resulting in better system reliability. For a multiphase voltage regulator, the SC1218 driver, FETs, inductor, and supply decoupling capacitors in each phase have to be considered as a unit. For the SC1218 driver, the following guidelines are typically recommended during PCB layout: a) Place the SC1218 close to the FETs for shortest gate drive traces and ground return paths; b) Connect decoupling capacitor as close as possible to the VIN pin and the PGND pin. The trace length of the capacitor on the VIN pin should be no more than 0.2" (5mm); and c) Locate the bootstrap capacitor close to the SC1218.
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PWM
To phase node
To bottom FET
R VIN
C VIN
Fig. 12. Component placement for SOIC-8
VIN PWM
CBST
To Top FET
RVIN
To Phase Node
RDRN CVIN
To Bottom FET
EN
Fig. 13. Component placement for MLPQ-8.
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SC1218
POWER MANAGEMENT Outline Drawing - SOIC-8
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc .069 .053 .010 .004 .065 .049 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.35 1.75 0.25 0.10 1.65 1.25 0.31 0.51 0.25 0.17 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 8 0 8 0.10 0.25 0.20
A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A C bxN bbb A1 C A-B D e D
h h
H GAGE PLANE 0.25
c
SEE DETAIL SIDE VIEW
NOTES: 1.
A
L (L1) DETAIL
01
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Land Pattern - SOIC-8
X
DIM
(C) G Z C G P X Y Z
NOTES: 1.
DIMENSIONS INCHES MILLIMETERS
(.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40
Y P
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A.
2.
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SC1218
POWER MANAGEMENT Outline Drawing - MLPQ-8, 3 x 3mm
A
Top View
D
B
PIN 1 INDICATOR (LASER MARK)
E
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A .032 .040 A1 .000 .002 .008 BSC A2 .012 b .007 .118 BSC D .071 D2 .059 .071 E2 .059 .118 BSC E e .026 BSC L .012 .016 .020 K .008 8 N 0 0 12 aaa .003 .008 bbb 0.08 1.00 0.00 0.05 0.20 REF 0.19 0.30 3.00 BSC 1.50 1.80 1.50 1.80 3.00 BSC 0.65 BSC 0.30 0.40 0.50 0.20 8 0 12 0.08 0.20
0
A2 SEATING PLANE
A aaa C A1 D2 e/2
Bottom View
C
L E/2 E2 2 1
K
N e b
D/2
bbb
CAB
Land Pattern - MLPQ-8, 3 x 3mm
H
DIM
(C) K
DIMENSIONS INCHES MILLIMETERS
(.122) .089 .073 .073 .026 .014 .033 .156 (3.10) 2.25 1.85 1.85 0.65 0.35 0.85 3.95
GZ
Y X
P/2
C G H K P X Y Z
P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THE VIAS ON THE CENTER PAD SHOULD MAINTAIN THE GOOD THERMAL CONTACT OF THE DEVICE TO THE PCB GROUND PLANE.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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